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Download Analog circuit design : high-speed clock and data recovery, by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier PDF

By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

Analog Circuit Design comprises the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit layout. every one half discusses a particular to-date subject on new and worthwhile layout principles within the sector of analog circuit layout. each one half is gifted through six specialists in that box and cutting-edge info is shared and overviewed. This ebook is quantity 17 during this winning sequence of Analog Circuit Design.

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Additional info for Analog circuit design : high-speed clock and data recovery, high-performance amplifiers, power management

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Monotone C1 Ideally equalized channel C-1 a) b) Monotone C2 C3 C4 Fig. 7 Effect of the 0 dB boost equalizer on pulse peak Fig. 8 Pulse peak reduction by a 0 dB boost equalizer mV Boost effect on pulse peak 350 300 250 200 150 100 50 0 0 5 10 boost [dB] 15 20 The crosstalk originates from adjacent transmitting channels, thus starting from the same spectral content of the signal, but because coupled crosstalk is high-pass shaped, low-frequency components are suppressed. The result is that crosstalk energy, mainly present around Nyquist or beyond it, will be only slightly affected by an equalizer having 0 dB boost at Nyquist.

Figure 4 shows its block diagram. With each new step that is taken in the increase of data rates on serial links, the requirements for high frequency jitter generation become stricter. Basically, the generated jitter must scale with the reduction of the bit length. In a typical transmit module the generated random jitter will be mainly determined by the oscillator that generates the clock with which the serializer and line driver is clocked. A ring oscillator is the most practical and lowest cost implementation of an oscillator that can achieve relative high speeds.

Since this involves a very wide exploration of the design space that includes the whole system, there is a need for fast simulation/calculation times. This can be obtained High-level design High-level verification VHDL-AMS model Block specifications Block design Block layout Back annotation Bottom-up verificaton Block design Block layout Back annotation Block design Block layout Back annotation Tape-out Fig. 3 Top-down bottom-up development flow 40 J. Crols by using very generic first order behavioral models/descriptions for the blocks and use a mathematical signal processing tool.

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